Memory Latency

What is memory latency[^1] (sometimes translated as "memory timings")

The duration from when a CPU issues a memory read/write instruction to when it is executed, measured in clock cycles. For example, a Samsung 4GB memory module is labeled: "4GB 2Rx4 PC3-10600R-09-10-E1-P0". The R in 10600R indicates that the memory latency is: 15-15-15

Knowledge Points

Taking DDR5 16GB 2Rx8 memory as an example[^2]

[^2]: Data excerpted from the YouTube video How Does Memory Works

Rank

• x8 indicates that a single DRAM chip has an I/O bit width of 8 bits
• A non-ECC DDR5 memory rank is 64 bits, 64 ÷ 8 = 8, so one rank needs 8 DRAM chips
• Therefore, the memory module has a total of 8 × 2 = 16 DRAM chips

Bank & Bank Group

• Each DDR5 DRAM chip has 8 Bank Groups
• Each Bank Group has 4 Banks
• Each Bank has 65536 rows, also called Wordlines
• Each Bank has 8192 columns, also called Columns
• A Bank in a DRAM chip is a storage plane composed of 1C1T cells, which can be thought of like Excel cells. A Bank has 8192 columns and 65536 rows, and each cell only stores 0 or 1.

Read/Write Operation Addresses in Bank

• 31 bits; using 110 11 0000110011100111 1100110010 as an example
• The first 3 bits (valid range 0-7) select which Bank Group
• Bits 4-5 (valid range 0-3) select which Bank within the Bank Group
• The next 16 bits (valid range 0-65535) indicate which column in a Bank, i.e., which wordline
  • Row Address Strobe - RAS
• The last 10 bits (valid range 0-1023) indicate which 8 data bits among the 8192 cells in a wordline
  • Column Address Strobe - CAS
  • Q: Why 10 bits of address, selecting 8 data bits?
  • A: 2Rx8 means the Bank I/O width is 8 bits. The 8192 columns are divided into 1024 contiguous groups of 8 cells each. The Column Address actually indicates the position of the first cell in each group of 8 columns.

Read/Write Process in a Bank

1. Row Close
2. Precharge Bitlines[^3]
3. Row Open
4. Column Address Select/Multiplex
5. Access 1T1C Cells Read/Write Data

As mentioned in the previous section, after the memory chip receives a set of 31-bit addresses and selects the Bank Group and Bank, it closes all wordlines in that Bank — this is the Row Close. Then it precharges all column bitlines, charging each Cell to 0.5V. Due to the capacitor, Cells that previously held a 1 remain 1 after precharge, and Cells that held a 0 remain 0. This process is called Precharge Bitlines, and it prevents data loss caused by electron leakage from the Capacitor in 1C1T Cells. After precharging, the 16-bit address selects and Opens the Row, then the 10-bit address selects 1 group out of 1024 (8 cells) via the Column Multiplex, and finally data is read from or written to the 1C1T Cell.

[^3]: Bitlines refer to the lines connecting a column of 1T1C cells; they correspond to wordlines, which connect the rows.

Latency

As mentioned earlier, RAM latency is expressed as three consecutive numbers, such as 15-15-15. To illustrate the difference, let's use 15-16-17 as an example.

• CAS
  • Column Address Strobe
  • The latency of selecting 8 consecutive bits from among 8192 columns in a memory chip
• tRCD
  • RAS to CAS Delay
  • The latency from the start of row addressing to the start of column addressing
• tPR
  • The latency of Precharge Bitlines
• Clock Cycles - clock cycle
  • A clock cycle is defined as the reciprocal of the frequency
  • But for DDR (Double Data Rate) memory, the nominal frequency is twice the clock frequency
  • Suppose a DDR5 memory module has a frequency of 4800 MHz
  • One clock cycle is: 1s / (4,800,000,000 Hz / 2) x 10^9 = 0.417 ns
• CAS latency: 15 x 0.417 ns = 6.255 ns
• tRCD latency: 16 x 0.417 ns = 6.672 ns
• tPR latency: 17 x 0.417 ns = 7.089 ns